1. Field
Embodiments relate to a data decoding apparatus and method for reducing a bandwidth.
2. Description of the Related Art
Generally, a processor block and a hardware block included in a decoding apparatus transmit or receive data with respect to an external memory during decoding.
When an amount of data between the processor block and a memory increases, a data transmission rate is reduced due to direct memory access (DMA) setting latency and access latency, thereby deteriorating system performance.
When at least two processor blocks and hardware blocks simultaneously request data transmission from the memory, data transmission may not be performed according to an optimum decoding order. Therefore, decoding may be impeded.
A general decoding apparatus, using pluralities of processor blocks and hardware blocks, may access the memory using a DMA controller provided in each processor block and each hardware block. Since the general decoding apparatus usually transmits data in a rectangular form, after transmission of data of one horizontal line, an overhead is generated until transmission of next line data, accordingly increasing the data transmission time.
When at least two processor blocks or hardware blocks request transmission from the memory in the general decoding apparatus, data transmission is performed only according to an order set by the DMA controller because communication between the decoding apparatus and the memory is not defined.